7431 - AXI4 Interconnect Module: Why the interconnect return DECERR response when perform AXI4 read/write transaction?

Description:

There is a known issue found in AXI4 Interconnect Module where VHDL parameter assignment is not parse correctly results in wrong internal address decoding.

This issue is manifest when the IP is generated in VHDL.

Solution:

To workaround this issue, user should generate the IP in Verilog instead of VHDL.

This is scheduled to be fixed in new release of Lattice Propel Software Tool.

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7431 - AXI4 Interconnect Module: Why the interconnect return DECERR response when perform AXI4 read/write transaction?

7431 - AXI4 Interconnect Module: Why the interconnect return DECERR response when perform AXI4 read/write transaction?

Related Articles

7393 - AHB-Lite Bridge IP Cores: Do Lattice AHB-Lite Bridges support write strobes?

7379 - RISC-V MC CPU IP Core: Does RISC-V AHBL bus support burst transaction?

7754 - RISC-V MC v2.7: Cache Enabled Causing Intermittent Read Corruption

7501 - RISC-V CPU IP Core: How to achieve cache coherency with RISC-V CPU

7283 - System Memory IP: Does using the Output Register on System Memory IP (AHBL/AXI interface) ensure functionality for the RISC-V MC processor?