7393 - AHB-Lite Bridge IP Cores: Do Lattice AHB-Lite Bridges support write strobes?

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• 7379 - RISC-V MC CPU IP Core: Does RISC-V AHBL bus support burst transaction?

  Configuration of the RISC-V MC CPU caches is static based. Lattice currently do not support dynamic configuration of caches Lattice cache related API is limited to flushing instruction cache and invalidating data cache. The RISC-V MC perform burst ...

• 7501 - RISC-V CPU IP Core: How to achieve cache coherency with RISC-V CPU

  RISC-V cacheable address is configurable in MC, and fixed in RX. The RISC-V core is implementing write through policy, both the cache and destination value will be updated when store operation happen. This imply that CPU store operation will write to ...

• 7755 - RISC-V IP: Does the RISC-V Processor Support Vectored Mode Interrupts?

  Description Only RISC-V RX balanced mode and advanced mode support vectored interrupt table. Other RISC-V variant does not support vector interrupt mode. Resolution For RX core, user may find the macro in riscv.h Change it to MTVEC_MODE_VECTORED and ...

• 7406 - RISC-V CPU IP Core: Do Lattice RISC-V supports exception trap handler when writing data to an invalid address?

  Description: RISC-V SM(v1.5)/MC(v2.5) CPUs currently only support trap handler for read access error. When CPU read from an invalid instruction/data address range, it will cause an exception which trigger the trap handler. However, if CPU write to an ...

• 7431 - AXI4 Interconnect Module: Why the interconnect return DECERR response when perform AXI4 read/write transaction?

  Description: There is a known issue found in AXI4 Interconnect Module where VHDL parameter assignment is not parse correctly results in wrong internal address decoding. This issue is manifest when the IP is generated in VHDL. Solution: To workaround ...