Description: Lattice AHB-Lite Bridge IP Cores are based on AMBA3 specification which does not support write strobes. This applies to the following Bridges IP: AHB-Lite to AXI4 Bridge AXI4-to AHB-Lite Bridge AHB-Lite Interconnect AHB-Lite Feedthrough
The Feedthrough IP allows you to export the specific AMBA bus out from the Lattice Propel Builder system to the higher-level module. Please refer to FPGA-AN-02072-1.0: Lattice RISC-V Embedded Design Guidelines for more information on the application ...
The LatticeMico32 debugger is accessed using the Lattice USB download cable. Other Lattice tools like ispVM System, Reveal, and Orcastra also use the USB download cable. During development it is common to build and download new FPGA bitstreams. New ...
Description: RISC-V SM(v1.5)/MC(v2.5) CPUs currently only support trap handler for read access error. When CPU read from an invalid instruction/data address range, it will cause an exception which trigger the trap handler. However, if CPU write to an ...
Description: This error will only be observed when performing Open OCD debugging. A hang will be observed while doing a step-through debugging. This is caused a bug on the python script that generates the IP RTL. There is a NUM_OF_TIMERS parameter on ...