5405 - iCEcube2: Why there are errors when instantiating (VHDL) SB_RAM modules from iCEcube2 Technology Library?
Solution:
When doing VHDL instantiations of SB_RAM modules, the user should provide component declarations. Below is an example for the SB_RAM512x8 module:
component SB_RAM512x8
GENERIC (
INIT_0 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_8 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_9 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port(
RDATA : out std_logic_vector(7 downto 0);
RADDR : in std_logic_vector(8 downto 0);
RCLK : in std_logic;
RCLKE : in std_logic;
RE : in std_logic;
WADDR : in std_logic_vector(8 downto 0);
WCLK : in std_logic;
WCLKE : in std_logic;
WDATA : in std_logic_vector(7 downto 0);
WE : in std_logic
);
end component;