5518 - How to instantiate differential inputs in VHDL?

5518 - How to instantiate differential inputs in VHDL?

For differential inputs, users can refer to the example below:

COMPONENT SB_IO IS

GENERIC(
PIN_TYPE : std_logic_vector(5 downto 0) := "000000";
IO_STANDARD: string := "SB_LVDS_INPUT"
);
PORT(
PACKAGE_PIN : in std_logic;
LATCH_INPUT_VALUE : in std_logic;
CLOCK_ENABLE : in std_logic;
INPUT_CLK : in std_logic;
OUTPUT_CLK : in std_logic;
OUTPUT_ENABLE : in std_logic;
D_OUT_0 : in std_logic;
D_OUT_1 : in std_logic;
D_IN_0 : out std_logic;
D_IN_1 : out std_logic;
):
END COMPONENT SB_IO;

Only the positive pin will need to be inserted into this primitive. When the positive pin is inserted, the negative pin will automatically be assigned by the software. 

 

The assignment of sb_lvds is somewhat misleading in iCEcube2 when a device does not support LVDS standards (such as iCE40 UltraPlus). 

 

In the Radiant Software, which has the Device Constraint Editor, the pin settings can be changed.