ERROR - <E0005> Unknown Object 'CLOCK/CE/LSR NET' 'sclk'.
ERROR - <E0005> Unknown Object 'CLOCK/CE/LSR NET' 'clocking/clkos'.
ERROR - <E0005> Unknown Object 'CLOCK/CE/LSR NET' 'sclk2x'.

There are three FREQUENCY preferences for the above three clocks in your preference file.

FREQUENCY NET "sclk" 200.0 MHz PAR_ADJ 40.0 ;
FREQUENCY NET "clocking/clkos" 400.0 MHz PAR_ADJ 80.0 ;
FREQUENCY NET "sclk2x" 400.0 MHz PAR_ADJ 80.0 ;

When resynthesizing your design, the synthesized netlist may not include the same clock net names listed in your preference file, and that will cause the errors to be generated. This usually happens from the synthesis process when your design hierarchy or your design itself gets changed. The physical preferences including the FREQUENCY preference must be updated according to the revised hierarchy. Synthesis tools also tend to change some clock net names although the design has only a minor change. Therefore, track and check the synthesis tool's net name changes and your design hierarchy changes. Update the LPF file accordingly. Pay close attention to the clock net name changes. All those new name/path information on the clock nets and physical preferences can be found in the mapper (Design Summary -> Number of Clocks in the .mrp file) and physical preference (PGROUP names in the .prf file) files after the map process.

The example below shows how the net names can be changed:

FREQUENCY NET "sclk_c" 200.0 MHz PAR_ADJ 40.0 ;
FREQUENCY NET "my_top/clocking/clkos" 400.0 MHz PAR_ADJ 80.0 ;
FREQUENCY NET "my_top/sclk2x" 400.0 MHz PAR_ADJ 80.0 ;

The "sclk" clock net name is changed to "sclk_c" by the synthesis tool in the first preference. The other two preferences are revised because the hierarchy has been changed in your project.