Description: There is a known issue in Byte to Pixel IP version 1.5, which it causes the MIPI data packets missing. Solution: There is no planned fix for version 1.5. Please upgrade the IP to version 1.6 or above.
RGB666 is only packed, thus, can only see data type 1E. The user can still use RGB666 loosely packed using RGB888 since the mapping are the same. For the loosely packed, it need to zero out input bits [7:6], [15:14] and [23:22]. In pixel-to-byte GUI, ...
The fv_i and lv_i signals are only for CSI-2 mode, and unused in DSI mode. The user can leave it undriven if they are using DSI mode. If, however, they are using it for CSI mode, these signals should indicate frame valid and line valid pulses. The ...
Our CMOS to DPHY IP expects explicit syncs from the upstream device. From the BT.1120 spec, it looks like it send EAV & SAV code which has the embedded sync information. Our existing IP cannot support this. To support BT.1120, the customer would need ...
Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...
Lattice Technical Support Expectation Please be advised that highest priority for Lattice Technical Support will be given to 1. Software which is not working as expected or suspected bugs. We recommend that customers use the latest software tools and ...
Title: PCIe DMA in Ring Buffer Operation Mode Cannot Be Stopped Unexpectedly Issue Description: When the PCIe DMA is configured to operate in Ring Buffer DMA mode for continuous transfers, the DMA operation cannot be stopped unexpectedly. If a device ...
Glitch Fliter is used to prevent short-duration events of glitches, This is used to prevent False tripping on noise in a system. GLITCHFilter in device constraints , enables 1ns glitch filtering.
Description: In simulating designs for Lattice devices under Lattice Radiant, this error may appear if there is no GSR instantiated in the testbench. Solution: There is no planned fix for this simulation issue. To work around this, please instantiate ...