7151 - Radiant: How to encrypt the RTL for the entire design?
7151 - Radiant: How to encrypt the RTL for the entire design?
Description:
Please try checking on this using IP packager. The user guide is available as soon as you click help on the IP package stand-alone tool. Check FPGA-UG-02197.
In Radiant, the synthesis and post-synthesis processes are a combined process under "Synthesize Design". When you run synthesis using the standalone version of Synplify Pro, this version generates a .vm file which will be used to run post-synthesis ...
Changes to the post PAR design are generally refereed to as Engineering Change Orders, or ECOs. The changes are directly written into the Native Circuit Description (.ncd) database file without requiring that user go through the entire design ...
Description: We do not have a linter feature on Radiant. The RTL code is checked by the software when either updated or has been inserted in the project and then gives the appropriate message result (info/warning/error) on the output window. ...
Description: In Diamond and Radiant 2023.2 SP1 and older, while using LSE as the Synthesis Tool, the HDL Parameter in Active Implementation options may not take effect. Solution: This is a known issue for VHDL designs. See the following code: ...
Description: The opendrain I/O properties can be done on RTL using synthesis attribute (SynplifyPro). Solution: VHDL example: entity counter is Port ( rst,clk : in std_logic; o: out std_logic_vector(0 to 3); myoutput: out std_logic); attribute ...