Radiant and VHDL: How to enable open drain on I/O using RTL code?

Radiant and VHDL: How to enable open drain on I/O using RTL code?

Description:
The opendrain I/O properties can be done on RTL using synthesis attribute (SynplifyPro).

Solution:

VHDL example:

entity counter is
    Port ( rst,clk : in std_logic;
           o: out std_logic_vector(0 to 3);
   myoutput: out std_logic);
   
attribute OPENDRAIN: string;
attribute OPENDRAIN OF myoutput,o: signal is "ON";
end counter;
architecture count_arch of counter is
   signal count : std_logic_vector(0 to 3);
    begin
myoutput <= '0' when (rst='1') else 'Z';

Verilog Example:
module count( c,
clk,
rst,
en,
myoutput
);

  input clk,rst,en; 
  output [7:0]c;
  output myoutput /*synthesis OPENDRAIN = "ON"*/;
  reg [7:0]c;

assign myoutput = en ? 1'b0 : 1'bz;


When viewed in Signal/Pad report and Logical View, it can be seen that the open drain setting is recognized by the sysconfig properties.