Why Does Nexus LMMI Programming Have a ~65 MHz Minimum Pulse Width Clock Limit?

Why Does Nexus LMMI Programming Have a ~65 MHz Minimum Pulse Width Clock Limit?

Description:
  1. On Nexus devices, the LMMI programming fabric, which is shared across multiple IP blocks such as PLL, D‑PHY, and PMU—supports a Maximum LMMI programming clock (LMMICLK) frequency of approximately 65MHz.
  2. This frequency limit applies globally to the shared LMMI fabric, not to any single IP instance. As a result, all LMMI-based programming interfaces connected to the core fabric are subject to the same Minimum Pulse Width (MPW) LMMICLK constraint, including but not limited to the PLL.
  3. The effective Maximum LMMICLK frequency is determined by the slowest LMMI client within the shared fabric. Because all clients operate on the same core fabric level LMMI infrastructure, the most timing‑critical IP sets the upper bound for the entire fabric.

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