ODDRX1 Latency on Nexus Devices
Issue Description
ODDRX1 has approximate 2-3 clock cycle delay before the data will come out.
Affected Devices
- LFCPNX
- LFD2NX
- LFD2NX-35
- LFD2NX-65
- LFMXO5
- LFMXO5-35T
- LFMXO5-65T
- LIFCL
- UT24C
- UT24CP
Conclusion
The observed behavior where data changes take two clock cycles to reflect on the output is valid and expected. This is not a bug; it is the actual the primitive’s response based on how it was designed.
To work effectively with ODDRX1 in dynamic environments:
- Avoid changing data mid-cycle. If possible, align data updates to occur on clock edges, preferably at the beginning of a new data frame.
- Use a data valid signal to indicate when the output is stable. This allows downstream logic to sample data only after the full pipeline delay has been accounted for.
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