Hold Time Violations When Compiling EtherCAT with Single-Axis Motor Control Reference Design in Lattice Radiant 2025.2.1
Description
When you compile FPGA-RD-02342: EtherCAT with Single-Axis Motor Control Reference Design in Lattice Radiant 2025.2.1, Place & Route may report persistent hold-time violations even though setup timing closes with comfortable margin.
After running Place & Route on EtherCAT with Single-Axis Motor Control Reference Design in Radiant 2025.2.1, the timing report shows hold-slack failures even though setup is met by a comfortable margin. A typical failing signature looks like:
- Setup slack: meets by several hundred picoseconds (large positive margin)
- Hold slack: fails by ~-200 ps (typically 1–3 paths)
- Path topology: FF → LUT → FF inside the EtherCAT IP region of the design
The failure persists across multiple seeds and is not resolved by:
- Enabling Pipelining and Retiming
- Setting Impose hold time violation correction
- Setting Fix hold over setup
- Moving set_false_path constraints between .pdc and .sdc
This issue is due to Lattice Radiant routing engine in 2025.2.1 does not budget enough hold slack on certain FF→LUT→FF paths inside the EtherCAT IP region of FPGA-RD-02342 and does not take the detour routes required to close the small (~-200 ps) hold violations. The post-route setup margin remains healthy, confirming this is a routing-side hold-budgeting limitation rather than a placement, IP, or clock-uncertainty issue.
Resolution
- A Radiant 2025.2.1 software patch is required to compile FPGA-RD-02342 with clean hold timing.
- Please submit an Existing Software Patch request and reference this FAQ to request for: Patch 31302.
- The patch resolves the hold violations while preserving the original setup margin, and the design closes timing across multiple seeds.
- The fix is also planned for inclusion in a future official Radiant release.
Reference
- FPGA-RD-02342 — EtherCAT with Single-Axis Motor Control Reference Design User Guide