Description: Erase, Program, Verify Quad 1 enables that QE bit to '1'. In general, there are two (2) requirements/steps to enable booting from external SPI Flash through x4 (QUAD Mode) Step 1 - Convert the bitstream file into hex (Quad I/O read mode) ...
Assuming the frequency of the SPI Flash is not the limiting factor, there are two factors affecting CCLK frequency setting of Lattice ECP2M device in SPI Flash configuration mode: 1. fMAXSPI This is the maximum frequency that the internal ...
If booting up from internal NVCM, the sequence of events after power up is provided below (Note: Timing numbers are prorated from full chip simulation.): 1. After the analog POR is triggered at around 800 mv for Vcc and 1.5 V for Vccio, digital delay ...
See below for steps on how to perform Dual-Boot in MachXO5-NX Background: The current implementation of Dual-Boot is that the JUMP table is found at Address 0.
The LatticeXP2 can be setup to operate in dual boot mode. Dual boot mode permits the LatticeXP2 to attempt to load a "working" configuration bitstream, and if that bitstream fails to properly configure the FPGA for a "golden" or "failsafe" bitstream ...