5603 - Platform Manager II: How to read the fault logs from an external SPI Flash?
Description:
Please check document TN1277. Here's an excerpt from the document:
"The fault log data stored in the external flash can be read via the SPI interface. In the case where the external memory is connected to the primary SPI port, Diamond Programmer can be used to read and save the Fault Log Records from the JTAG interface."
Related Articles
Radiant Programmer: What is Erase, Program, Verify Quad 1 operation used for?
Description: Erase, Program, Verify Quad 1 enables that QE bit to '1'. In general, there are two (2) requirements/steps to enable booting from external SPI Flash through x4 (QUAD Mode) Step 1 - Convert the bitstream file into hex (Quad I/O read mode) ...
1869 - Platform Manager 2: How do you reset the I2C interface on Power Manager II devices?
It is not necessary to explicitly reset a Power Manager II's I2C interface. Because the I2C interface in this product family is a slave device, it will always be responsive to the SCL and SDA control signals generated by an I2C master. For example, ...
105 - How can I determine if a LatticeXP2 FPGA configured from internal flash or from an external SPI flash?
The LatticeXP2 can be setup to operate in dual boot mode. Dual boot mode permits the LatticeXP2 to attempt to load a "working" configuration bitstream, and if that bitstream fails to properly configure the FPGA for a "golden" or "failsafe" bitstream ...
7315 - MACHXO3: Why I cannot perform SPI programming after enable dual boot to configure from external SPI flash
Description: MACHXO3 device share the same SPI SysConfig ports for both SSPI and MSPI configuration mode. The Configuration(CFG) MSPI is designed to be bus friendly, i.e. when it's not actively booting, all MSPI pins are tri-stated. It's possible to ...
103 - Can the LatticeXP2 use encrypted configuration bitstreams supplied by an external SPI Master or SPI Slave?
The LatticeXP2 provides two methods to supply non-volatile programming images into the FPGA configuration memory. The first method employs an on-chip flash memory that is read and loaded at power-up or image refresh. The second method allows an ...