5325 - Nexus/MachXO2/XO3/XO5/ECP5/ECP5-5G: What is the Hitless I/O behavior if IO is set to open-drain?
If the Hitless I/O is pulled up to a user defined value when the IO is set to open-drain, the TransFR option will not hold the user defined IO value. This is a limitation of the Hitless IO feature since the user modified the IO setting to be open drain rather than the default IO values
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5154 - MachXO3: In doing background programming with transFR enabled, how does the pin re-configured from being an input to bidi and it's behavior as bidi when device is power cycled?
The I/O electrical properties like drive strength, slew rate, open-drain, pull modes are preserved from the Initial Programming. These settings are not cleared unless the device is power-cycled or loaded with a new bitstream to overwrite these ...
6574 - MachXO2/MachXO3: Why is the IO state locked during TransFR Operation of MACHXO3 device?
Description: The IO electrical properties like Drive strength, Slew, Open-Drain, and Pullmodes are preserved (carried over) from the initial configuration. These settings are not cleared unless the device is Power-cycled or loaded with a new ...
6514 - All Nexus Family: How to set DONE, INTN and PROGRAMN pins as GPIO in Nexus Family?
To use these Configuration pins as an IO, follow the steps below: 1.) The First step is to set this pins to DISABLE (in this case INITN_PORT, DONE_PORT and PROGRAMN_PORT to DISABLE). After running the design flow up to export files, a .fea file will ...
7152 - EIO for Nexus FPGAs: What does EIO function mean in the pinout file and the purpose of the pins?
'EIO' function mentioned in the pinout file refers to 'Early I/O Release' enhanced configuration function. Our Nexus device supports this feature to allow the I/O that reside in the I/O Banks on the left and right of the device to release earlier so ...
7149 - Nexus Devices: What is the maximum SPI Flash size that Nexus devices can boot?
Nexus devices can boot up to 4 Gb as long as Control register 1 bit 14 (32-bit SPIm Commands) and bit 17(32-bit SPIm Address) is set to 1. See below: