5108 - Why is there no clock output on MCLK pin after FPGA programs when using USRMCLK macro in the design?

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  The MachXO2 has 2 hardened SPI cores tied to the internal FPGA configuration logic. These cores can be accessed through an internal bus interface (wishbone) by instantiating the Embedded Function Block (EFB) element in HDL code. The SPI cores have a ...

• 5287 - Should the USRMCLK be used only when the device is in MSPI mode or if it is needed to disable the MasterSPI port to generate your own MasterSPI controller?

  To enable the same SPI pins used in configuration, to User SPI, the pins need to be persistent. The user SPI control should connect the User SPI signals to those pins. The MCLK is not a GPIO pin, and can be used in User SPI. The MCLK can select ...

• 7204 - How to properly Configure FPGA with on-board programmer using HW-USBN-2A/B?

  When configuring FPGA using HW-USBN-2A/B with an on-board programmer, especially Lattice evaluation boards, users must disable the on-board programmer (FTDI) by pulling the reset pin to LOW to have a successful operation. This is to avoid channel ...

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• 1263 - Can the PROGRAMN pin be held low for a period of time during power-up to prevent the FPGA from configuring?

  Yes, PROGRAMN pin can be used to hold FPGA from configuring. The are cases where user is using SPI programming mode and would like to control the exact time to begin configuration with PROGRAMN pin. Lattice FPGA enter configuration mode when one of ...