2357 - How can I guarantee that the state machine will return to the known state from any invalid state?
A state machine is implemented with the encoding state registers after synthesis. And all states of the state machine will be represented by values of the state registers. But some values of the state register can be set to undefined states, i.e., so-called invalid states. For example, the valid states for one-hot encoding state machine will have one bit of the state register set to 1 and others set to 0. Any other values of the state register are regarded as invalid. For binary encoding state machine, there still exists the invalid states if the state number is not 2 to the power of N. Usually the synthesis process will ignore the invalid states during the state machine optimization. This means the state machine may not return to a known state once it enters an invalid state. The steps below will prevent this from happening.
In Synplify Pro, the value of safe for the syn_encoding attribute can be used to solve the problem. The following is an example:
in Verilog:
reg [2:0] state/* synthesis syn_encoding="safe" */;
always @(posedge rst or posedge clk)
if (rst)
state <= 0;
else
case (state)
0: if (din)
state <= 1;
1: state <= 2;
2: state <= 3;
3: state <= 4;
4: state <= 5;
5: state <= 6;
6: state <= 0;
endcase
in VHDL:
signal state : std_logic_vector(2 downto 0);
attribute syn_encoding : string;
attribute syn_encoding of state : signal is "safe";
begin
process (rst, clk)
begin
if (rst = '1') then
state <= "000";
elsif rising_edge(clk) then
case state is
when "000" => if (din = '1') then
state <= "001";
end if;
when "001" => state <= "010";
when "010" => state <= "011";
when "011" => state <= "100";
when "100" => state <= "101";
when "101" => state <= "110";
when "110" => state <= "000";
end case;
end if;
end process;
end architecture RTL;
When syn_encoding is safe, the state machine can be reset from an invalid state to its reset state. It makes the state machine more robust.