Processors & Embedded Systems | RISC-V MC

RISC-V MC
7754 - RISC-V MC v2.7: Cache Enabled Causing Intermittent Read Corruption
Description In Propel 2024.2, when RISC-V MC IP Core v2.7 is enabled with cache, user may observe intermittent read corruption when read from non-cacheable memory range. For example: RISC-V MC CPU with cache enabled copy from External Flash to System ...
7379 - RISC-V MC CPU IP Core: Does RISC-V AHBL bus support burst transaction?
Configuration of the RISC-V MC CPU caches is static based. Lattice currently do not support dynamic configuration of caches Lattice cache related API is limited to flushing instruction cache and invalidating data cache. The RISC-V MC perform burst ...

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