What are the considerations when simulating Lattice Diamond devices with VHDL test bench?

What are the considerations when simulating Lattice Diamond devices with VHDL test bench?

Description: This knowledge database will provide an aided guide when considering simulating Lattice Diamond devices with VHDL test bench top file.

Problem: Simulation errors as shown below:
Unresolved reference to 'GSRNET' in GSR_INST.GSRNET. 
Unresolved reference to 'PURNET' in PUR_INST.PURNET.

Solutions:
A. Simulation under Lattice Diamond environment requires to instantiate Power Up Reset and Global Reset parameters.
This can be done in the top-level design or testbench design files as follows:
In Verilog:
PUR PUR_INST(.PUR(1'b1));
GSR GSR_INST(.GSR(1'b1));

In VHDL:
PUR_INST:   PUR port map (PUR=>'1');
GSR_INST:   GSR port map (GSR=>'1');

B. If no error due to undeclared GSR_INST and PUR_INST, the next step is to recompile simulation libraries.
The device library has to be recompiled to map it to VHDL libraries as the tool will automatically be directed to the simulation library of Verilog.

To avoid this issue, perform the following steps:
(1) Close any active Aldec Riviera/ModelSim/QuestaSim window.
(2) Locate built-in Tcl Console on Diamond Software (located on the lower left portion).
(3) Run this script into the Tcl Console: cmpl_libs -sim_path {C:/lscc/diamond/3.14/modeltech/win32loem} -device ecp5u -lang vhdl
Note: Change the device name if you are using another FPGA device.
(4) After running the script, re-run Aldec Riviera/ModelSim/QuestaSim and redo the simulation. The VHDL test bench should compile without an issue and should be able to run the simulation.