Lattice does not have any data regarding the gate counts for a device. Only the Look-Up Table (LUT) counts are available for a device. The reason is that an LUT can be configured in an end design either as INVERTER or 4 input AND gate. The actual ...
The IO behavior of each Lattice device family could be unique. Some of the device families support pull and bus keeper circuitry for each individual pin, some support such function on a global basis, while others have different pull condition for ...
Most Lattice FPGA devices provide a complimentary output feature which allows a single ended buffer to provide its compliment on a different pin without using any FPGA logic resources or user routing. To enable this complimentary path the user needs ...
Yes. However, there are considerations to keep in mind when choosing pins. The MachXO2 implements two aspects of PCI buffers independently: PCI-level compliant inputs/outputs PCI complaint internal clamps. MachXO2 implements PCI-level compliant ...
Whether an I/O pad is hot-socketable or not is determined by the location of the pad instead of the bank where the pad is included. All general purpose I/O pads located on the top and bottom sides of LatticeECP3 devices are hot-socketable.These are ...