7214 - Avant-E: How to enable RISC-V software debug for Avant-E device
Description:
User is required to implement soft JTAG to enable RISC-V debug in Avant-E early silicon.
Solution:
Please follow below step to enable debug with Soft-JTAG. The pin assignment is based on Avant-E Evaluation Board.
- Create an Avant-E RISC-V RX based SoC Project from Propel Builder/Propel SDK
- Choose board template - Avant-E Evaluation Board
- The Avant-E board template should have the following automatically setup in place
- Enable RISC-V debug port in Propel Builder
- In RISC-V IP wizard, choose Debug enable
- Export the JTAG interface in Propel Builder
- Assign JTAG signals to GPIO in Radiant. TCK assigned to PCLK to prevent potential implementation failure
- Connect HW-USBN-2B cable to J10 header:
- TCK/SCLK connect to pin 3
- TMS connect to pin 13
- TDI/SDI connect to pin 7
- TDO/SDO connect to pin 9
- VCC connect to pin 1(VCC_3V30)
- GND connect to pin 11
- Note: Technically you may assign any GPIO ports to TMS, TDI, TDO and any PCLK ports to TCK for your convenience, but some of the assignment might cause mapping error or par error, which is software bug and will be fixed in Radiant 2023.1.
- The project provides a feasible connection, you may use it directly if not modify the post-synthesis constraint file.
- Debug configuration in Propel SDK:
- Detect Cable: "Lattice HW-USBN-2B Ch A"
- Don't "Scan Device", leave it blank
- Change the "Config options" in "Debugger" Tab to:
- -c 'echo "DEBUG_ENABLE=${DEBUGENABLE}"' -c "set target ${DEVICE}" -c "set tck ${TCKDIV}" -c "set port ${PORT}" -c "set channel 14" -c "set cmdlength 32"
- -f interface/lattice-cable.cfg -c "set RISCV_SMALL_YAML {${ProjDirPath}/src/cpu0.yaml}" -f target/riscv-small.cfg
- Start debugging, ignore the following error: "Err: can not found the device from device family database, use default value to access this device"
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