2603 - How long can the user evaluate the DDR3 IP core on the hardware system using the bitstream generated in the evaluation mode without a license? Can they continue the evaluation when the evaluation timer expires?
All Lattice IP cores provide the hardware evaluation capability using
the IP hard timer. The IP hard timer usually runs up to four hours and
its running time is not determined by the IP cores but depends on the
target device's internal OSC (oscillator) rate. Since the OSC rate is
not fixed due to the PVT (process, voltage and temperature) variations,
each FPGA may have a different timer running time, and we do
not characterize the exact runtime for the IP hard timer. It is known to
be roughly between 2~4 hours. It will give ample time to evaluate most DDR3 IP core-based designs.
Once the IP
hard timer expires, the FPGA goes to the hardware reset mode. The user cannot
wake up the FPGA by asserting the system reset signal. The only way to
reset the IP hard timer and re-evaluate the DDR3 IP core is to
reconfigure the FPGA by downloading the bitstream again.