1264 - How to check if the hardware timer is instantiated in Lattice FPGA devices?

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• 2603 - How long can the user evaluate the DDR3 IP core on the hardware system using the bitstream generated in the evaluation mode without a license? Can they continue the evaluation when the evaluation timer expires?

  All Lattice IP cores provide the hardware evaluation capability using the IP hard timer. The IP hard timer usually runs up to four hours and its running time is not determined by the IP cores but depends on the target device's internal OSC ...

• 3950 - Can I evaluate a Lattice FPGA IP without a license?

  The user can generate the bitstream for most Lattice FPGA IPs without any license, but with a "hardware timer" that enables them to use the bitstream only for a limited time before the internal timer resets. Also, the user cannot do the Timing ...

• 420 - Which Lattice devices contain Beryllium?

  Lattice has provided our customers with 2 documents that describe what materials are used in our devices. The first is the "Package Device Material Breakdowns" document which shows the breakdown by weight of the various different substances contained ...

• 4669 - How to find what all Lattice IP cores are supported by Lattice FPGA families?

  User can refer "Product Selector Guide" document to check which all IP cores are supported by Lattice FPGA families. User can get the "Product Selector Guide" from respective Product page under documentation section > Information Resources > Product ...

• 1105 - What is the moisture sensitivity level (MSL) of Lattice devices?

  All Lattice through-hole mount devices are 28-pins or fewer and have an MSL of 1. For surface mount devices, please refer to respective package MSL in FPGA-TN-02041 - Solder Reflow Guide for Surface Mount Devices.