Modelsim Lattice Edition: Simulation: This phenomenon can occur if you force the simulator into an incorrect timescale. If a PLL is generated with a phase shift on the outputs, and the simulator is forced to an incorrect timescale by using a "-t " command, the phase of the PLL output clock may look like it's constantly moving with respect to its PLL input.
To correct this, remove any -t directives in your simulation command. The default timescale needs to be honored or reduced (-t 1fs) in order to correctly simulate the PLL with a phase shift.