7406 - RISC-V CPU IP Core: Do Lattice RISC-V supports exception trap handler when writing data to an invalid address?
Description: RISC-V SM(v1.5)/MC(v2.5) CPUs currently only support trap handler for read access error. When CPU read from an invalid instruction/data address range, it will cause an exception which trigger the trap handler. However, if CPU write to an ...