VCS simulation error: Error-[XMRE] Cross-module reference resolution error

Description:

When using the VCS simulator, this error may appear if you have not included GSR in your testbench.

Solution:

GSR_INST and PUR_INST should come from testbench so this should be included manually.

See below for example: vcs -sverilog -timescale=1ns/100ps v2k tb.v GSR.v PUR.v +libext.vp machxo3l_black_boxes-vcs.vp

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VCS simulation error: Error-[XMRE] Cross-module reference resolution error

VCS simulation error: Error-[XMRE] Cross-module reference resolution error

Related Articles

Verilog Compiler Simulator (VCS) simulation: Error-[URMI] Unresolved modules

iCEcube2 Modelsim: Error: (vsim-3067) Debug module called from nondebug module

Modelsim for Diamond 3.13: "Error: (vsim-3043) Unresolved reference to I2C_WAKE"

ECP5 / Diamond 3.14: Why does my design get a Map device oversize error related to PLL for LFE5U-12F in with Diamond 3.14, but completes map successfully in earlier releases of Diamond software?

OEM Modelsim: Fatal: (vsim-3693) The minimum time resolution limit (10fs) in the Verilog source is smaller than the one chosen for SystemC or VHDL units in the design. Use the vsim -t option to specify the desired resolution.