Resolving PLL Clock Constraint Discrepancies in Radiant for MachXO4 and MachXO4D

Resolving PLL Clock Constraint Discrepancies in Radiant for MachXO4 and MachXO4D

Summary

When a PLL is configured to generate several output clocks from a single input, the frequencies reported in post-synthesis static timing analysis may not match the frequencies configured in the PLL IP. This is a reporting issue in the timing analysis flow. The PLL hardware operates as configured, and simulation confirms the correct output frequencies. This article explains the cause and documents the recommended constraint adjustment that restores accurate timing reports while retaining full use of the PLL.

Symptoms

With only the primary input clock constrained, the auto-generated generated-clock constraints may cause the timing report to show frequencies substantially lower than configured. For a 40 MHz input configured for 40 MHz, 10 MHz, and 0.1 MHz outputs, the report may show approximately 3.077 MHz, 0.769 MHz, and 0.400 MHz respectively, while the primary input clock itself is reported correctly. Simulation of the same design returns the configured frequencies.


Why the reported frequencies differ

The PLL does not divide the input clock directly. It first multiplies the input to produce a high-frequency internal VCO signal, and the output dividers then operate on that VCO frequency. In a configuration with a 40 MHz input and a 520 MHz VCO, a divide-by-13 on the VCO yields the correct 40 MHz output.

The auto-generated generated-clock constraints name the input clock as the source but apply the VCO-referenced divider values without the corresponding multiplication term. Static timing analysis therefore applies the divider directly to the input clock and reports a frequency that is low by exactly the VCO-to-input ratio. The device configuration itself is unaffected.

The recommended action is to supply the missing multiplication term explicitly in the generated-clock constraints. This aligns the timing report with the configured PLL output frequencies, requires no change to the PLL IP configuration, and does not alter device behaviour, so the PLL remains fully usable in the current design and tool version.

The multiplier is the ratio of the VCO frequency to the input clock frequency for the specific configuration in use; it is not a fixed value of 13. The divider is the total VCO-referenced division for that output, which for a cascaded output is the product of the dividers in the chain.

For a 40 MHz input with a 520 MHz VCO, giving a multiplier of 13:

  1. create_generated_clock -name {clkop_pin} -source [get_pins {u_pll/lscc_pll_inst/u_pll/CLKI}] \
  2.     -multiply_by 13 -divide_by 13 [get_pins {u_pll/lscc_pll_inst/u_pll/CLKOP}]

  4. create_generated_clock -name {clkos_pin} -source [get_pins {u_pll/lscc_pll_inst/u_pll/CLKI}] \
  5.     -multiply_by 13 -divide_by 52 [get_pins {u_pll/lscc_pll_inst/u_pll/CLKOS}]

  7. create_generated_clock -name {clkos3_pin} -source [get_pins {u_pll/lscc_pll_inst/u_pll/CLKI}] \
  8.     -multiply_by 13 -divide_by 5200 [get_pins {u_pll/lscc_pll_inst/u_pll/CLKOS3}]

The CLKOS3 divider of 5200 reflects the cascaded path, being the product of the preceding stage divider and the CLKOS3 divider, rather than the CLKOS3 divider alone.




Expected critical message when using the workaround

With the constraints applied, Map and Place and Route report critical:

  1.  70001942 (Multiplier/divider of user clock doesn't match PLL setting u_pll0/lscc_pll_inst/u_pll/CLKOS/3),
indicating that the user clock multiplier or divider does not match the PLL setting. This message is an expected consequence of the same reporting behaviour and does not indicate an invalid PLL configuration. The timing report will show the frequencies matching the PLL IP settings, and the implemented design is unaffected. Users should record this acknowledgement in their design review notes so that the message is not raised again as an unresolved item at sign-off.

If the constraints produce pin resolution errors

Applying the override may produce warnings:

  1. 1026001 (../source/impl_1/impl_1.sdc (2): Can't resolve object 'e_clk_gen_wrapper/e_clk_gen/lscc_pll_inst/u_pll/CLKOP' in constraint 'create_generated_clock -name {CLK_40M} -source [get_pins e_clk_gen_wrapper/e_clk_gen/lscc_pll_inst/u_pll/CLKI] -divide_by 13 -multiply_by 13 [get_pins e_clk_gen_wrapper/e_clk_gen/lscc_pll_inst/u_pll/CLKOP]') and
  2. 1027013 (Warning 1027013 No pin matched '\e_clk_gen_wrapper/e_clk_gen/lscc_pll_inst/u_pll/CLKOP'.),
reporting that no pin matched or that an object cannot be resolved. These warnings are unrelated to the reporting defect and to the Radiant version. They arise from the point in the flow at which the constraint is applied.

If the constraint is placed in a pre-synthesis .sdc file, it is passed to synthesis before mapping, at which stage the PLL IP is still a black box and a pin path such as .../lscc_pll_inst/u_pll/CLKOP does not yet exist as a resolvable object. Moving the same constraint into a post-synthesis .pdc file applies it at Map, where the hierarchy is fully instantiated and the pin paths resolve correctly, producing the corrected frequencies without these warnings.

PLL cascade configuration

The PLL IP GUI may present more than one cascade source for a given output. For cascade configuration, follow the sysCLOCK PLL description in the MachXO4 datasheet, which documents the CLKOS2 to CLKOS3 cascade path. Users considering a cascade arrangement not described in the datasheet should contact Lattice Technical Support before committing to it in a production design.

The frequency reporting behaviour described in this article is independent of cascade configuration. Outputs taken directly from the VCO and outputs derived through a cascade both exhibit the same misreport, so cascading is neither the cause nor a contributing factor.

Best practice

  • Apply the multiplier and divider constraints in a post-synthesis .pdc file, using the VCO-to-input ratio for the configuration in use, rather than relying on the auto-generated constraints alone.
  • Derive the multiplier from the actual VCO and input frequencies of the configuration; do not reuse the value 13 from the example.
  • For cascaded outputs, use the product of the dividers along the cascade chain as the divider value.
  • Treat critical 70001942 as expected once the constraints are applied, and note it in the design review record.
  • Confirm output frequencies in simulation as an independent check of the PLL configuration.

Conclusion

The discrepancy is confined to how output frequencies are reported in static timing analysis. The PLL generates the configured frequencies, and neither the IP configuration nor the implemented design requires modification. Supplying the VCO-to-input multiplier alongside the existing divider in a post-synthesis .pdc file restores accurate reporting and allows full use of the PLL in the current tool version, with critical 70001942 understood as an expected consequence rather than a configuration error. This adjustment is the advised approach for designs in progress. A correction to the reporting model is planned for a future Radiant release, after which the constraints may be reverted to the auto-generated form. For assistance with a specific configuration, contact Lattice Technical Support.