6880 - Modelsim: How can I make simulation pass when I encounter the minimum resolution FATAL error (VSIM-3693)?

To proceed with simulation, users need to manually add -t ns in vsim such as in the line 19 in the mdo file:

vsim -voptargs=+acc -t ns -L work -L pmi_work -L ovi_<device> <test_bench_top>

Example:

vsim -voptargs=+acc -t ns -L work -L pmi_work -L ovi_lfcpnx Nexus_ADC_top_tb

This allows the simulation to start and with this, users need to update the wizard to include -t parameter in vsim command.

Related Articles
7019 - OEM Modelsim: Fatal: (vsim-3693) The minimum time resolution limit (10fs) in the Verilog source is smaller than the one chosen for SystemC or VHDL units in the design. Use the vsim -t option to specify the desired resolution.
Description: When running simulation wizard directly on a design which includes a PLL, a fatal error is encountered as given below ** Fatal: (vsim-3693) The minimum time resolution limit (10fs) in the Verilog source is smaller than the one chosen for ...
1242 - Simulation: Modelsim: What does "Fatal : Obsolete library format for design unit" Modelsim error mean?
Simulation: Modelsim: If the simulation libraries or your design files are compiled with an older version of Modelsim (for example, Modelsim 6.3) and are now being loaded (VSIM) into a newer version of Modelsim (for example, Modelsim 6.5), you will ...
Diamond RAM_DP_TRUE IP QuestaSim simulation error: Fatal: (vsim-3483) Delay in signal assignment is not ascending. # Fatal error at a source-protected location
Decription When simulating the default RAM_DP_TRUE IP, you may experience the following error: # ** Fatal: (vsim-3483) Delay in signal assignment is not ascending. # Time: 105 ns Iteration: 1 Instance: /tb/u1/test_ram_0_0_0_0 File: nofile Line: ...
111 - ModelSim: Fatal: vsim-3381 Obsolete library format for design unit.
Description: Fatal errors may be encountered when a design is loaded in Modelsim (VSIM). Designs using pre-compiled Lattice device models like the Physical Coding Sublayer logic, like the PCSD in the LatticeECP3 FPGA, are compiled for a specific ...
1204 - Simulation: Modelsim: Modelsim failed with the error message:"# ** Error: (vsim-3170) Could not find './work.StimModule_Unknown'."
Description: Modelsim will produce this error when it cannot find a design to be loaded. Error: "# ** Error: (vsim-3170) Could not find './work.StimModule_Unknown'." Workaround: To workaround this, user required to check the module name at the top ...

6880 - Modelsim: How can I make simulation pass when I encounter the minimum resolution FATAL error (VSIM-3693)?

6880 - Modelsim: How can I make simulation pass when I encounter the minimum resolution FATAL error (VSIM-3693)?

Related Articles

7019 - OEM Modelsim: Fatal: (vsim-3693) The minimum time resolution limit (10fs) in the Verilog source is smaller than the one chosen for SystemC or VHDL units in the design. Use the vsim -t option to specify the desired resolution.

1242 - Simulation: Modelsim: What does "Fatal : Obsolete library format for design unit" Modelsim error mean?

Diamond RAM_DP_TRUE IP QuestaSim simulation error: Fatal: (vsim-3483) Delay in signal assignment is not ascending. # Fatal error at a source-protected location

111 - ModelSim: Fatal: vsim-3381 Obsolete library format for design unit.

1204 - Simulation: Modelsim: Modelsim failed with the error message:"# ** Error: (vsim-3170) Could not find './work.StimModule_Unknown'."