You can add multiple directories in the "Verilog Include Search Path" in Design implementation, you can define them as (Example): C:/Users/cmeala/Desktop/CASES/Include Case/Path1;C:/Users/cmeala/Desktop/CASES/Include Case/Path2 then try using ...
In Diamond version 3.14, there is a bug where it incorrectly limits the number of PLLs in the device to 0 for LFE5U-12F. Example error message: ERROR - (device oversize error). The number of PLL components needed (1) exceeds the number available. ...
To give a background on this, in a single SLICE, there can be two possible registers/FFs. Map does the SLICE utilization calculation solely based on the number of registers/FF per SLICE. Architecturally, there are 2 FFs/registers and 2 LUTs per ...
Description: When using the DELAYD primitive for MachXO2, there is an error message such as this: ERROR - Dynamic delay component 'delayd_0' cannot drive component 'Z_out_pad_RNO' Solution: According to the MachXO2/XO3 usage model, the dynamic delay ...
Description: When user design is compiled (Synthesis --> Bitstream) a Warning shown below is encountered WARNING -Security project file open Error! Security feature is turned OFF! Solution: The warning is valid and is just providing message that the ...