7707 - CertusPro-NX/System Memory v2.3.0: Why is the maximum Memory Address Depth was reduced in v2.3.0.

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• 7755 - RISC-V IP: Does the RISC-V Processor Support Vectored Mode Interrupts?

  Description Only RISC-V RX balanced mode and advanced mode support vectored interrupt table. Other RISC-V variant does not support vector interrupt mode. Resolution For RX core, user may find the macro in riscv.h Change it to MTVEC_MODE_VECTORED and ...

• 7283 - System Memory IP: Does using the Output Register on System Memory IP (AHBL/AXI interface) ensure functionality for the RISC-V MC processor?

  Description: Setup violations in path between RAM and CPU over new extended memory CPU system. Path Begin : ...

• 7406 - RISC-V CPU IP Core: Do Lattice RISC-V supports exception trap handler when writing data to an invalid address?

  Description: RISC-V SM(v1.5)/MC(v2.5) CPUs currently only support trap handler for read access error. When CPU read from an invalid instruction/data address range, it will cause an exception which trigger the trap handler. However, if CPU write to an ...

• 7501 - RISC-V CPU IP Core: How to achieve cache coherency with RISC-V CPU

  RISC-V cacheable address is configurable in MC, and fixed in RX. The RISC-V core is implementing write through policy, both the cache and destination value will be updated when store operation happen. This imply that CPU store operation will write to ...

• 7608 - Propel Builder: How to export AMBA bus out from Lattice Propel Builder system with a valid memory-mapped address range to the higher-level module.

  The Feedthrough IP allows you to export the specific AMBA bus out from the Lattice Propel Builder system to the higher-level module. Please refer to FPGA-AN-02072-1.0: Lattice RISC-V Embedded Design Guidelines for more information on the application ...