7223 - Radiant 2023.2 SP1: Why does Lattice PCIe X4 IP v2.3.1 ModelSim simulation using Radiant 2023.2 SP1 show an error "Fatal: (vsim-3381) Obsolete library format for design unit. Design unit ../RadiantIPLocal/latticesemi.com_ip_pcie_x4_2.3.1/testbench/

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• 1242 - Simulation: Modelsim: What does "Fatal : Obsolete library format for design unit" Modelsim error mean?

  Simulation: Modelsim: If the simulation libraries or your design files are compiled with an older version of Modelsim (for example, Modelsim 6.3) and are now being loaded (VSIM) into a newer version of Modelsim (for example, Modelsim 6.5), you will ...

• 111 - ModelSim: Fatal: (<em style="font-family: &quot;Courier New&quot;;">vsim-3381) Obsolete library format for design unit.</em>

  Description: Fatal errors may be encountered when a design is loaded in Modelsim (VSIM). Designs using pre-compiled Lattice device models like the Physical Coding Sublayer logic, like the PCSD in the LatticeECP3 FPGA, are compiled for a specific ...

• ModelSim error on IP instantiation: (vsim-3033) Instantiation of 'MULTADDSUB36X36' failed. The design unit was not found.

  Description: This error can occur when the Simulation tool uses the wrong libraries for your design. Solution: Go to the ModelSim File menu, then select Source Directory... Select the directory where your work library is located. Then, go to the ...

• OEM Modelsim: How do i fix the errors encountered below? Error: (vsim-3033) Instantiation of 'DPHY' failed. The design unit was not found.

  Description: When running simulation on the Lattice Simulation tool, the tool may encounter an error relating to the design unit. This is encountered when the needed libraries are not added in the simulation project. Solution: 1) Go to Modelsim ...

• OEM Modelsim: Fatal: (vsim-3693) The minimum time resolution limit (10fs) in the Verilog source is smaller than the one chosen for SystemC or VHDL units in the design. Use the vsim -t option to specify the desired resolution.

  Description: When running simulation wizard directly on a design which includes a PLL, a fatal error is encountered as given below ** Fatal: (vsim-3693) The minimum time resolution limit (10fs) in the Verilog source is smaller than the one chosen for ...