7156 - Propel: How to perform Memory Allocation in RISC-V

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• 7053 - Propel: Why I unable to run debugger with Propel SDK on my RISC-V Project?

  Description: 1. RISC-V reset vector is fixed at address 0x00000000, thus instruction memory must start at address 0x0. 2. RISC-V instruction port is a read only port. To run debugger with Propel SDK, the SoC design must support writes to the ...

• 7326 - Propel: Why does the RISC-V debug session hang during exception handling?

  Description: RISC V CPU instruction/data manager consists of exception handling routine in the BSP source: ..\src\bsp\driver\riscv_mc\interrupt.c The API is a standard RISC V practice where it prints out the failure based on the mcause register when ...

• 7214 - Avant-E: How to enable RISC-V software debug for Avant-E device

  Description: User is required to implement soft JTAG to enable RISC-V debug in Avant-E early silicon. Solution: Please follow below step to enable debug with Soft-JTAG. The pin assignment is based on Avant-E Evaluation Board. Create an Avant-E RISC-V ...

• 6910 - Propel / RISC-V SM/MC/RX: What is the Range, Width, and Size mean on a Memory Map CSV file?

  For a memory map, Range is the maximum bit width of each address. Width here is the number of addresses. The Size of each register is the number of bits on each register. So Width is not the sum of sizes of each register. The Size of the register can ...

• 7502 - Propel SDK GDB OpenOCD Debugger: How do user connect RISC-V debugger to FPGA device without downloading software image?

  This feature is supported in Propel SDK v2024.1, feature describe as "attach to running target" in debugger startup tab. User may refer to below User Guide for more information: Lattice Propel 2024.1 SDK User Guide - FPGA-UG-02211-1.0 - Appendix E. ...