6842 - SGMII for Nexus FPGAs: What is the usage of "clk_gddr_o"?

The purpose of clk_gddr_o is to serve as clock source to another chip outside the FPGA.

Do take note that this output clock is synchronous with ser_tx_o.

Another thing, the clock source of clk_gddr_o is coming from the PLL + DDR module (with synchronizer).

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6842 - SGMII for Nexus FPGAs: What is the usage of "clk_gddr_o"?

6842 - SGMII for Nexus FPGAs: What is the usage of "clk_gddr_o"?

Related Articles

7002 - PCIe for Nexus FPGAs: Where to download the PCIe Demo driver source code for Linux and Windows?

6250 - PCIe for Nexus FPGAs: In PCIe X4 IP Core, I have selected AHB_LITE as the Data Interface Type. What is the clock domain for this interface?

6900 - PCIe for Nexus FPGAs: How can the PCIe configuration space settings in the RTL of the demo be interpreted?

967 - LatticeECP2/M/LatticeECP3: Does the LatticeECP2M and LatticeECP3 SGMII and Gb Ethernet PCS IP "xmit_autoneg" port indicate autonegotiation [xmit] status as defined by IEEE 802.3 ?

7743 - How to implement Gigabit Ethernet in Certus-NX, CertusPro-NX, MachXO5-NX and CrossLink-NX FPGAs?