6137 - Lattice FPGAs: How to interpret the Date Code breakdown?

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• 7486 - Where can I find the 3D model of Lattice FPGAs?

  Solution: Users can search the 3D Model of Lattice FPGAs at below link. There are open source libraries that may have the 3D Model, PCB Footprints and Symbol files as the packages are standard and widely used. The link: ...

• 543 - Do Lattice FPGAs support Spread-Spectrum Clocking (SSC)?

  There are two aspects to SSC support: SSC generation and SSC reception. Only the LatticeSC family provides SSC generation support. Refer to TN1099, "LatticeSC sysCLOCK PLL/DLL User’s Guide" for more information (search for "spread spectrum"). ...

• 2598 - Can Lattice FPGAs use a general purpose I/O to assert it's own PROGRAMN pin?

  Lattice does not recommend using the FPGA's general purpose I/O to assert its own PROGRAMN pin. There is risk the FPGA may not restart after the first attempt to assert the PROGRAMN pin. The PROGRAMN pin can inadvertently be pulled low, which can ...

• 1100 - How can I use the complimentary outputs in Lattice FPGAs? <br>

  Most Lattice FPGA devices provide a complimentary output feature which allows a single ended buffer to provide its compliment on a different pin without using any FPGA logic resources or user routing. To enable this complimentary path the user needs ...

• 1151 - <p>What is the best way to divide a clock by 2 in Lattice devices?</p>

  There are several different ways you could divide an incoming clock signal by 2. You could use the internal clock divider that is provided in the LatticeECP2/M, LatticeXP2, and LatticeSC/M FPGA devices. The LatticeECP2/M and LatticeXP2 each have 2 ...