6073 - CSI-2/DSI D-PHY RX IP: How can we connect CSI2 RX to Hard DPHY1 instead of DPHY0 which is the default location?

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• 6304 - Lattice Diamond: By using the hard D-PHY of Crosslink, why does the FREQUENCY PORT declared in the constraint file changed to FREQUENCY NET in the timing analyzer which then generates a warning message?

  For hardened blocks like hardened DPHY, the timing analyzer cannot read the hardened blocks once constraining them. As a recommendation, the designer should constrain the other clocks that are actually used to clock soft logic, like the byte clocks ...

• 6603 - Radiant: How to perform IP re-generation using ipgen?

  First, run "ipgen.exe -h" from the tcl console to view all the command options as shown below. usage: ipgen.exe [-h] [-o OUTPUT_DIR] [-proj_dir PROJ_DIR] -ip IP_MODULE_DIR [-cfg IP_CONFIG_FILE] [-skip_uniquify SKIP_UNIQUIFY_HDL] [-cfg_value ...

• 5229 - CrossLink / DPHY to CMOS IP v1.2: Why am I not able to place the GPIO/IO_ports on bank0 in CrossLink while using DPHY to CMOS IP?

  Description: When placing CMOS IO to Bank0, P&R errors are encountered indicating of wrong placement in the I/O bank0. Solution: In CrossLink, IP has been updated by adding ODDR hard block at the output side to enhance the design to support more than ...

• 7772 - Diamond RAM_DP_TRUE IP QuestaSim simulation error: Fatal: (vsim-3483) Delay in signal assignment is not ascending. # Fatal error at a source-protected location

  Decription When simulating the default RAM_DP_TRUE IP, you may experience the following error: # ** Fatal: (vsim-3483) Delay in signal assignment is not ascending. # Time: 105 ns Iteration: 1 Instance: /tb/u1/test_ram_0_0_0_0 File: nofile Line: ...

• 7121 - Lattice Radiant: How do I constrain my Soft DPHY Data lanes?

  You may refer to Section 5.22.2 (DDR Input Setup and Hold Time Constraints) of CrossLink-NX High-Speed I/O Interface Technical Note (FPGA-TN-02097-1.8) while referencing the values found in Section 3.17 (External Switching Characteristics). For ...