6065 - CrossLink: Is DPHY0 output possible after MIPI input to DPHY1? (Like BYPASS)

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• 5399 - Aldec Simulation: No MIPI data after executing the run simulation and #KERNEL errors occur 

  Description: When using the Aldec Simulator, the following errors can occur when simulating MIPI. #KERNEL: ERROR : Fff: Clock after input divider is out of range #KERNEL: ERROR : Fvcout: Clock before output divider is out of range #KERNEL: ERROR : ...

• 1051 - Modelsim Lattice Edition: Simulation: Why does the simulation show the output clock phase constantly shifting with respect to the input clock in a PLL?

  Modelsim Lattice Edition: Simulation: This phenomenon can occur if you force the simulator into an incorrect timescale. If a PLL is generated with a phase shift on the outputs, and the simulator is forced to an incorrect timescale by using a "-t " ...

• 2775 - Diamond: How can I add a net that directly connects with an input signal and an output signal in Diamond Schematic Editor ?

  In Lattice Diamond Schematic Editor, each input signal and output signal should be connected with an input port and an output port respectively and be named uniquely, and each net has only a single name, therefore, you cannot connect the net with ...

• 1774 - Diamond: How can the user set the DELAYB cell to add delay to an input port when a single register exists between the input and output ports?

  When only one register is present between the primary input and the primary output ports, that register is automatically placed in the output PIO cell . This prevents the DELAYB cell from being used in the input PIO cell even when user add the DELAYB ...

• 1871 - LatticeXP2: Can the PROGRAMn and DONE pins be used as general purpose input/output?

  The PROGRAMn and DONE pins on the LatticeXP2 can be either dedicated for device configuration, or they can become General Purpose I/O (GPIO). The CFG0 input pin to the FPGA controls how these pins behave. You can find full details in LatticeXP2 ...