6017 - MachXO2: There are no timing parameters specified in the datasheet for the XO2 slice Flip-Flop (ex. CLK vs LSR recovery time, CLK vs LSR removal time, and LSR minimum pulse). Where can I find the timing values?

• Related Articles

• 4529 - Diamond 3.5: Does recovery and removal timing analysis is performed on Flip-Flop when <strong>Infer GSR </strong>(Global Set/Reset)&nbsp;option is set to True in Strategy&nbsp;setting?

  Solution: No, it does not. Recovery and removal timing analysis is performed in design if GSR-True in design. Timing analysis is not applied to any signal attached to the GSRN net on the devices. So if the reset on the device is routed via the GSRN ...

• 1150 - Diamond: What does the M or Minimum Speed grade mean in a Lattice&nbsp;I/O timing report?&nbsp;<br>

  The M or Minimum Speed grade device appears to be faster than the fastest speed grade in the I/O timing report and the term "Minimum Speed grade" can be a bit confusing. For starters, it does NOT mean the slowest silicon device. The term refers to ...

• All Nexus / Radiant 2023.1 or earlier: How are the clock-to-out max and clock-to-out min values on the I/O Timing Analysis report calculated?<div><br></div>

  Clock-to-out max corresponds to the arrival time of the data of the external timing path when setup time is analyzed. Clock-to-out min corresponds to the arrival time of the data of the external timing path when hold time is analyzed. If there are ...

• 5819 - Diamond: Why did TRACE not detect a violation in the LSR pin, but during simulation, it was detected?

  The static timing engine does static timing analysis only. The LSR pin is not a clock pin and the pulse width requirement on this pin must be guaranteed by the designer. The static timing engine does not check for the pulse width on the LSR pin. ...

• Why there are designs passing on MAP showing a good SLICE utilization percentage but failing PAR showing unplaced SLICEs due to 100% SLICE utilization percentage?

  To give a background on this, in a single SLICE, there can be two possible registers/FFs. Map does the SLICE utilization calculation solely based on the number of registers/FF per SLICE. Architecturally, there are 2 FFs/registers and 2 LUTs per ...