5931 - ICE40: Where can we change the configuration oscillator clock frequency for iCE40 Devices?

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• 6897 - Radiant / PLL IP version 1.4.0 and newer: What alternatives can users use for PLL version 1.4.0 reference clock input if they cannot use the onboard oscillator (12 MHz) of the CrossLink-NX Evaluation Board as the clock input?

  Users have a couple of options for their design to use the CrossLink-NX evaluation board: 1. Use an external clock from a different clock pin: Instead of using the onboard oscillator, users can connect one of the other PCLK pins as input to the FPGA ...

• 4753 - iCE40 UltraPlus: Error: "The system clock frequency on the PLL output Port A must be between 4 and 133.33 MHz."

  For Phase and Delay compensation modes of PLL, the PLL configuration tool of iCECube shows the following error: "The system clock frequency on the PLL output Port A must be between 4 and 133.33 MHz.". However, the data sheet indicates that the max ...

• 6441 - PLL for Nexus FPGAs: How to dynamically change the PLL output frequency?

  Description: On FPGA-TN-02095, locate Appendix C. PLL LMMI Operation. The user can access the PLL dynamic parameters through the use of LMMI (Lattice Memory Mapped Interface). Solution: If the user wants to vary the output frequency (for example ...

• 6430 - CertusPro-NX / ADC: Why is a PLL used to drive the ADC adc_clk_i pin and not directly driven by an oscillator output?

  Description:This article explains the reason ADC clock-in cannot be driven using an oscillator output in CertusPro-NX. Solution:In CertusPro-NX., the ADC clock input is hard-wired on the fabric to the 4th secondary output (CLKOS4) of the Lower Right ...

• 4736 - All Devices: How to improve the jitter value of the PLL clock output?

  Follow these recommendations to generate several clock signal outputs with minimum jitter: 1. Use the PLL and the ODDR clocked by the edge clock. 2. Use a clock source with less jitter. 3. Use dedicated clock input routing pins to assign the clock to ...