5700 - Crosslink: Why do I get 24 MHz even if I set the MCLK frequency of 48MHz in the MCLK frequency of Crosslink?

Crosslink: This is a known issue due to a hardware problem. The clock frequency is set to 48 MHz, but the clock divider always needs to be set to divide by 2, which means the actual frequency clock is only 24 MHz.

The reason is due to design constraints. The original plan was to run the clock at 48 MHz, but the default read clock from power up is too fast, so the plan to slow down the clock had been its next step.

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5700 - Crosslink: Why do I get 24 MHz even if I set the MCLK frequency of 48MHz in the MCLK frequency of Crosslink?

5700 - Crosslink: Why do I get 24 MHz even if I set the MCLK frequency of 48MHz in the MCLK frequency of Crosslink?

Related Articles

6894 - Diamond / Synplify Pro: Why is the Frequency for Synplify Pro Strategy Setting is set to 1 MHz when using the Area preset strategy?

2633 - How to use PAR_ADJ with FREQUENCY and set the ratio between the clock domains?&nbsp;

6071 - CrossLink: Why did I get 0x7F for a device ID instead of 0x15 when attempting to prgoram the SPI flash on MasterLink Board?

6806 - All Nexus / Radiant: Why can't users see reset signals on the timing analysis reports even without setting the set_false_path constraints?

1774 - Diamond: How can the user set the DELAYB cell to add delay to an input port when a single register exists between the input and output ports?

2633 - How to use PAR_ADJ with FREQUENCY and set the ratio between the clock domains?