5250 - MachXO3L: Is the nine-times programmability always true or does the number of program cycles for an "L" part depends on the size of the design, and therefore, configuration memory utilization?

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• 6166 - Does MachXO3L support program/erase as many times as MachXO3LF?

  Description: According to the Datasheet (FPGA-DS-02032), in Table 3.6. Programming/Erase Specifications, MachXO3L has a multi-time (max of 9 times) programmable NVCM while the MachXO3LF devices have reconfigurable Flash up to 100,000 write/erase ...

• 5811 - iCE40 LP: The NVCM programming spec frequently mentions wait times equivalent to a certain number of clock cycles even if SPI_SS_B pin is high. Does the master need to provide actual clocks in the SPI_SCK pin during these wait times?

  The master needs to provide clock pulses during those wait times where SPI_SS_B is high. Customers should be aware of this and they should incorporate this into their microcontroller firmware. The recent version of the NVCM programming specs ...

• 534 - MachXO: Why can't I scan or program the MachXO device on the MachXO Mini board after I programmed my pattern into the device?

  The MachXO JTAG pins on the MACHXO Mini board share the same traces with some generic IOs of the MachXO device (as shown on page 4 and page 2 of the schematic). If the new design patterns have signals driving out of these pins, they could potentially ...

• 6957 - MachXO3D: What is the architecture of TRNG( True Random Number Generator ) Feature?

  The TRNG feature architecture is a Hardware-based entropy source for true random data.

• 142 - What is a possible reason for the INITn pin going low while loading configuration image from SPI flash device?

  One possible reason for a configuration loading error can be the image content loaded into the SPI flash. Some serial SPI Flash devices do not guarantee the data integrity of the first few bytes during a read. To address the issue, the ...