431 - ispVM System: How is bitstream programming verification (Verify) performed within Lattice ispVM System?
The PLD programming verification with ispVM System performs a bit-for-bit compare of the device bitstream against the desired .JED file (as opposed to a less informational computed checksum comparison).
This is easily verified by viewing the log file (ispVM.log) after a Verify failure. For example:
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12/17/09 14:39:29
Device LC4256ZE: Verify Only
--------------Row--------------:
HDR 1
TDR 0
SDR 1592 TDI(00000000000000000000000000000000000...
Expected TDO(DFFFFE0FFFE71FCFF00FFBE73FFFF0FC1F0...
Received TDO(7FFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFF...
Bits Error 1592: Expected: 1 Received: 0
Bits Error 1590: Expected: 0 Received: 1
Bits Error 1569: Expected: 0 Received: 1
Bits Error 1568: Expected: 0 Received: 1
Bits Error 1567: Expected: 0 Received: 1
Bits Error 1566: Expected: 0 Received: 1
Bits Error 1565: Expected: 0 Received: 1
Bits Error 1549: Expected: 0 Received: 1
Bits Error 1548: Expected: 0 Received: 1
Bits Error 1544: Expected: 0 Received: 1
and more...
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