4044 - [ECP3]: Does the Tri-Rate Serial Digital Interface (SDI) IP support 2048x1080_24p?

The IP does not directly support 2K formats. However, you can define 2K as a custom standard in the IP GUI. Then the IP will support it.

The format detection part of the receiver does not identify the stream as 2048x1080, instead, it identifies all unsupported formats as Custom.

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2988 - [LatticeECP3]: Can Lattice High Definition Multimedia Interface/ Digital Visual Interface (HDMI/DVI) reference designs-RD1097 support more resolutions?
Yes. Some settings of Serializer-Deserializer (SerDes) are adjusted through Serial Communication Interface (SCI) to support more resolutions low up to 800x600@60Hz. "10B only" mode is used in SERDES for our High Definition Multimedia Interface/ ...
2393 - [LatticeECP3]: Can Lattice's reference design "HDMI/DVI Interface" support audio function?
With the reference design UG36-- "HDMI/DVI Interface", we provide raw data signals "rx_ade/rx_audio_ch0[3:0]/rx_audio_ch1[3:0]/rx_audio_ch2[3:0]". The user may get audio data by decoding the signals according to HDMI specification. To output audio ...
2392 - [LatticeECP3]: Can Lattice's reference design "HDMI/DVI Interface" support all resolutions defined in HDMI/DVI specification?
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4144 - For Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) Rx Design i.e RD1185, is there any minimum time period requirement for reset of FPGA ? Does it come out of reset after a valid Data clock (DCK) is available?
There are no requirements for the reset. It is an asynchronous logic reset.

4044 - [ECP3]: Does the Tri-Rate Serial Digital Interface (SDI) IP support 2048x1080_24p?

4044 - [ECP3]: Does the Tri-Rate Serial Digital Interface (SDI) IP support 2048x1080_24p?

Related Articles

2988 - [LatticeECP3]: Can Lattice High Definition Multimedia Interface/ Digital Visual Interface (HDMI/DVI) reference designs-RD1097 support more resolutions?

2393 - [LatticeECP3]: Can Lattice's reference design "HDMI/DVI Interface" support audio function?

2392 - [LatticeECP3]: Can Lattice's reference design "HDMI/DVI Interface" support all resolutions defined in HDMI/DVI specification?

6133 - CrossLink: Is there any reference design that uses 2 IP core solutions using CSI-2/DSI D-PHY Receiver and Byte to Pixel Converter?

4144 - For Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) Rx Design i.e RD1185, is there any minimum&nbsp;time period requirement for reset of FPGA ? Does it come out of reset after a valid Data clock (DCK) is available?

4144 - For Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) Rx Design i.e RD1185, is there any minimum time period requirement for reset of FPGA ? Does it come out of reset after a valid Data clock (DCK) is available?