1771 - MachXO: are the charge pumps and oscillators working after configuration? 

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• 5931 - ICE40: Where can we change the configuration oscillator clock frequency for iCE40 Devices?

  Solution: Depending on what software you are using, (Radiang Software or iCEcube2), you can change the configuration oscillator clock frequency using these steps. Radiant Software: Go to Project > Active Stratefy > Bitstream Settings > Oscillator ...

• 3767 - What is the limit of writing or reading of Single Port RAM for MachXO2 devices? Why can't I find the exact limit on how fast write or read from Single Port RAM can be done?

  The maximum frequency limit value for Single Port RAM depends on the speed grade and the type of the device (that is ZE/HC/HE). For example, in case of the MachXO2 Breakout Board (MachXO2-7000HE and speed grade 4), the maximum frequency limit of a ...

• 1686 - What is the impact and potential problems when the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet?  

  It is common for most of today’s FPGA’s to provide multiple PLLs to support the flexible clock requirements needed for today's complex system design. The PLL has a specific frequency operational range. For example, the LatticeXP2 datasheet indicates ...

• 5712 - MachXO3L: Does PLL clock outputs are glitch less when enabled or disabled via ENCLKO*?

  The output clocks are glitchless during enabled or disabled event through ENCLKO*.

• 4736 - All Devices: How to improve the jitter value of the PLL clock output?

  Follow these recommendations to generate several clock signal outputs with minimum jitter: 1. Use the PLL and the ODDR clocked by the edge clock. 2. Use a clock source with less jitter. 3. Use dedicated clock input routing pins to assign the clock to ...