1631 - What conditions can lead to a loss of multi-channel alignment on the XAUI PCS IP?

The loss of multi-channel alignment (MCA) in the XAUI PCS IP can be caused by two types of factors:

Any condition that can cause a burst of invalid 8b10b characters to the PCS/SERDES QUAD :

disturbing the SERDES inputs by physically breaking the line
stopping the reference clock to the PCS/SERDES QUAD
Corrupting data (invalid 8b10b characters).

A condition that can prevent the /A/ channel alignment character (K28.3) from simultaneously being received on all four lanes for 4 consecutive times. This condition causes the MCA logic in the XAU PCS IP to lose alignment as shown in the IEEE 802.3ae specification PCS deskew State diagram.

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1631 - What conditions can lead to a loss of multi-channel alignment on the XAUI PCS IP?

1631 - What conditions can lead to a loss of multi-channel alignment on the XAUI PCS IP?

Related Articles

2022 - Do Lattice XAUI PCS solutions only allow Ethernet frame sizes between 64 and 1518 bytes as specified in IEEE 802.3ae?

2367 - LatticeECP3: How does the RX loss of signal detection circuitry in the LatticeECP3 SERDES/PCS react to a constant value or a&nbsp;drop in&nbsp;signal condition on the SERDES serial inputs?

991 - In LatticeECP2M external LSM mode, how does the word aligner hunt for comma during word alignment?

697 - Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?

344 - For SERDES/PCS-based Lattice devices, can I use the CTC FIFO in the hard PCS even if I connect the PCS to the SGMII/GbE PCS IP?

2367 - LatticeECP3: How does the RX loss of signal detection circuitry in the LatticeECP3 SERDES/PCS react to a constant value or a drop in signal condition on the SERDES serial inputs?