1265 - Is there any non-volatile setting provided by the LatticeECP2/M to set permanent pull-up resistors on the I/O pins before the device is programmed?

• Related Articles

• 1033 - Do the unused I/O pins need to be grounded in a device?

  Lattice devices have weak internal pull-ups on all I/Os. So the I/O pins which are not used in the design do not need to be grounded or connected anywhere. Some of Lattice devices have global setting for pull-ups on IOs like On, Off or Bus Hold, and ...

• 4045 - iCE40 : What is the default status of I/O pins before the configuration of an <em>iCE40 </em>device?

  The default status of I/O pins before the configuration of an iCE40 device is tri-stated with a weak pull-up to VCCIO.

• 2263 - LatticeECP3:&nbsp; What is the proper use of termination resistors and internal coupling with the Lattice Serdes?

  Current Mode Logic (CML) buffers are used as the common interface to the SERDES/PCS. Internal input and output terminations are provided to simplify board level interfacing and AC coupling capacitors are available within the CML receiver. These allow ...

• 4686 - iCE 40: What is the recommended value for pull-up resistor on the&nbsp;user I/O&nbsp;pin of <b><font face="Courier">iCE40</font></b> devices?

  Solution: There is no recommended value for pull-up resistor on the user I/O pin, as it depends on the purpose of using the pin. If the pullup is to avoid keeping a pin floating, then any pull-up value is fine unless power is a requirement. In such ...

• 6996 - iCE40: Does Bank 3 have any internal pull-up resistors for iCE40?

  Details: GPIOs found in Banks have no internal pull-ups, only Banks 0-2 have internal pull-ups. Since they do not have any internal pull-up in Bank 3, we recommend tying the unused PIO pins in Bank 3 to a known logic or driving them with disabled ...