1024 - LatticeMicoSystem: What do I need to do to migrate from LatticeMico8 V2.4 to V3.1?
The LatticeMico8 had many changes and improvements made to the core between V2.4 and V3.1. The changes were made with an eye toward providing a more capable system while still maintaining the fundamental characteristics of the original releases. The changes made to the core do require you to make some modifications to your design.
- Assembly code
The V2.4 core only had the ability to assemble branch instructions that could span +511/-512 opcodes. The V3.1 core improved all branch instructions to permit a +2047/-2048 PC relative range. It is necessary to reassemble code written for V2.4 using the new isp8asm tool. Make sure you use the isp8asm tool that matches the LatticeMico8 HDL code.
- LatticeMico8 opcodes loaded from prom_init.hex
The output from the assembler must be in hexadecimal data format using the -vx switch. The prom_init.hexfile is used by ispLever to initialize the LatticeMico8 program store. The PROM_FILE passed parameter defines which hexadecimal data file to use. The synthesis tool can be configured to override the PROM_FILE passed parameter.
- Scratchpad RAM
The V3.1 core no longer automatically has 32 bytes of internal scratchpad RAM. It is up to you to instantiate any required scratchpad RAM. The scratchpad RAM is always considered to be external to the processor. Assembly code that was written for a combination of internal and external scratchpad RAM must be inspected to make sure the first 32 bytes in each memory space do not overlap.
- Memory Ready Input
The V3.1 core implements a READY input signal for port memory accesses and scratchpad memory accesses. If your design did not have an issue interfacing to external peripherals at V2.4 memory transaction speeds you can simply tie this signal to a constant '1'.
- Simulation
The simulation environment has changed quite a bit. This is due to the use of the Lattice Semiconductor PMI modules. It is best to review the TCL files in the simulation subdirectory to get direction on how to correctly establish a simulation environment for the V3.1 core.